Interconnect parasitic extraction is useful for analyzing signal propagation characteristics such as impedance mismatch and timing delays, as well as ground bounce in power distribution systems. The extraction of highly accurate interconnect parasitics, however, is difficult for many complex interconnect structures such as found in integrated circuits, electronic packages, and printed circuit boards, because of excessive processor and memory requirements.
For example, although three-dimensional (“3-D”) full-wave field solvers are known to provide high accuracy in calculating interconnect parasistics, less accurate two-dimensional (“2-D”) field solvers are generally employed in the design process to reduce processor and memory requirements to practical levels.
To further reduce parasitic extraction time during the design verification phase, a library of pre-computed RLGC (resistance “R”, inductance “L”, conductance “G”, capacitance “C”) functions for a number of 2-D canonical interconnect structures may be provided. When a 2-D cross-section of an interconnect matches that of a canonical structure in the library, the pre-computed information stored in the library can be used to quickly calculate RLGC coefficients for the interconnect.
Interconnect parasitics can be classified as being either area, lateral or fringe parasistics. Area parasistics involve interactions between top and bottom surfaces of two conductive elements disposed vertically with respect to each other. Lateral parasitics involve interactions between opposing side surfaces of two conductive elements disposed horizontally with respect to each other. Fringe parasistics involve interactions between side surfaces of one conductive element and a top (or bottom) surface of another conductive element disposed below (or above) it.
Various models for interconnect parasitic extraction have been used for generating an equivalent circuit or transmission line for simulating an interconnect. One RC model uses area resistance (“Ra”) and area capacitance (“Ca”) coefficients for generating an equivalent RC circuit. Another RC model uses fringe capacitance (“Cf”) as well as the area resistance (“Ra”) and area capacitance (“Ca”) coefficients. An RLC model, on the other hand, uses an area inductance (“La”) as well as the area resistance (“Ra”), area capacitance (“Ca”), and fringe capacitance (“Cf”) coefficients for generating an equivalent RLC circuit for simulating the interconnect.
None of these approaches, however, succeeds in extracting interconnect parasitic coefficients that accurately simulate interconnect frequency response over a wide range of operation like a 3-D full wave field solver does.